Sunday, May 26, 2013

Sidense memory IP cores are automotive-qualified

April 2, 2013 by  
Filed under News, Product News

Sidense Corp., a developer of Logic Non-Volatile Memory (LNVM) one-time programmable (OTP) memory IP cores, announced that the Company’s 1T-OTP macros for TSMC’s 180nm BCD 1.8/5V/HV and G 1.8/5V processes have met all of TSMC’s IP9000 Assessment program requirements.

Renesas and TSMC collaborating on MCU ecosystem

June 22, 2012 by  
Filed under Company News, Industry News, News

Renesas Electronics Corporation and TSMC are extending their microcontroller technology collaboration to 40 nanometer (nm) embedded flash (eFlash) process technology for next-generation automotive and consumer applications. Renesas previously agreed to outsource MCUs to TSMC using 90nm eFlash process technology.

Semico conference to “Focus on the IP Ecosystem”

April 3, 2012 by  
Filed under Company News, Industry News, News

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Semico Research Corporation will sponsor an Impact Conference, “Focus on the IP Ecosystem,” at the Doubletree Hotel in San Jose on May 16, 2012.

TSMC uses Synopsys Galaxy implementation platform for 28nm PVQ test chip

August 9, 2010 by  
Filed under Design, News, Product News

Synopsys said TSMC has successfully taped out a complex 28-nanometer (nm) Product Qualification Vehicle (PQV) test chip using Synopsys’ Galaxy™ Implementation Platform. Key features used to design the PQV test chip include 28-nm design rule support for place-and-route, interconnect process modeling, IEEE 1801-2009 (UPF)-based hierarchical low power flow, power-aware design-for-test (DFT) and advanced signoff capabilities.

ARM launches Cortex-M4 processor for high performance digital signal control

February 22, 2010 by  
Filed under Design, News, Product News

ARM has launched the Cortex™-M4 processor for automotive and other digital signal control (DSC) applications. Features include a single-cycle multiply-accumulate (MAC) unit, optimized single instruction multiple data (SIMD) instructions, saturating arithmetic instructions and an optional single precision Floating-Point Unit (FPU).