Synopsys universal DDR controllers improve performance and reduce cost of embedded DRAM interfaces

April 29, 2010  by  

Synopsys, Inc. has announced the availability of high-performance DesignWare® universal DDR protocol and memory controllers, both supporting the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards. The controllers make it easier for designers to integrate multiple DDR interfaces into one design with less risk and improved time-to-market.

The universal memory controller helps reduce both the latency and silicon area by up to 50 percent compared to Synopsys’ previous generations of DDR memory controllers, thus improving DRAM interface performance and reducing overall chip costs. The universal protocol controller provides efficient DDR control and protocol translation for applications without the need for a multi-ported memory controller. Both controllers deliver memory system performance of up to 2133 Mbps, the maximum data rate of the DDR3 standard, and offer a DFI 2.1-compliant interface to the DDR PHY.

The multi-port memory controller accepts memory access requests from up to 32 application-side host ports, each of which can be configured independently to be synchronous or asynchronous to the controller clock. The memory controller is also said to provide high memory bandwidth utilization through transaction reordering, bandwidth allocation per port, and quality-of-service (QoS) based arbitration for latency-sensitive and/or high-bandwidth traffic.

The single-port DesignWare universal DDR protocol controller is designed to optimize memory channel bandwidth utilization with reduced latency, allowing designers to implement a custom memory scheduler that is optimized for specific DRAM traffic patterns. The controller supports 1:1 or 1:2 clock frequency ratios between the controller and memory channel, enabling low latency in high-speed, general purpose process technologies and ease of timing closure in low power process technologies.

“As DDR SDRAM standards continue to proliferate, it is vital to provide designers with a DDR IP solution that can support the breadth of SDRAM options,” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “The new DesignWare Universal DDR protocol and memory controllers help designers address the critical latency and silicon area demands of advanced SoCs while simultaneously optimizing the utilization of the memory channel bandwidth.”

The DesignWare Universal DDR protocol and memory controllers are part of Synopsys’ comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, Mobile DDR and LPDDR2. The DesignWare DDR IP supports leading 130-nm, 90-nm, 65-nm, 55-nm and 45/40-nm technologies. Synopsys helps lower integration risk by providing high-quality DDR IP solutions that have been implemented in hundreds of applications and are shipping in volume production.


The DesignWare Universal DDR protocol and memory controllers as well as the complementary PHYs are available now. For more product information and video demonstrations of DesignWare DDR IP, visit:

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven interface and analog IP solutions for system-on-chip designs. Synopsys’ broad IP portfolio delivers complete connectivity IP solutions consisting of controllers, PHY and verification IP for widely used protocols such as USB, PCI Express, DDR, SATA, Ethernet, HDMI and MIPI IP including 3G DigRF, CSI-2 and D-PHY. The analog IP family includes Analog-to-Digital Converters, Digital-to-Analog Converters, Audio Codecs, Video Analog Front Ends, Touch Screen Controllers and more. In addition, Synopsys offers SystemC transaction-level models to build virtual platforms for rapid, pre-silicon development of software. With a robust IP development methodology, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: Follow us on Twitter at

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